Respuesta :
Answer:
the J and K inputs are tied to Vcc.
Explanation:
A J-K flip-flop can be defined as a gated set-reset (SR) flip-flop with an additional clock input circuit that is being used as a feedback to prevent any invalid or illegal output condition that may arise, when the set (S) and reset (R) inputs are equal to logic level 1.
Basically, in a set-reset (SR) flip-flop the set (S) should have a logic level output that is equal to 1 while the reset (R) has 0; these two levels as the name implies, are used to set and reset the device respectively.
A J-K flip-flop is being used as a divide-by-2 circuit when the J and K inputs are tied to Vcc i.e the ground voltage. Thus, the set and reset pins are not being used but are rather tied to Vcc in a divide-by-2 circuit.
The J and K inputs are tied with Vcc. Thus the option B is correct.
What is the J-K flip-flop?
The J-K flip-flop can be said as the gated set-reset with the additional clock input circuits that are used as feedback to prevent any invalid or illegal output condition that may arise, when the set (S) and reset (R) inputs are equal to logic level 1.
The flip-flop is being used as a divide by 2 circuits when the inputs are tied to the Vcc by the ground voltage. Thus, the set and then reset the pins that are not used but are rather tied to Vcc.
Find out more information about the J-K flip-flop.
brainly.com/question/917110.
