Assign the following timing attributes to the primitive gates in one-bit full adder in Functional
Analysis Part 1.
TINV = 10ps
TAND2 = TOR2 = 50ps
Apply the truth table to the inputs of the full adder, and find the minimum and maximum
propagation delays at the Carry-Out and Sum outputs, using `timescale-command in Verilog.
Show the minimum and maximum propagation delays in a timing diagram for all 8 cases, and
then tabulate them in an Excel table. Do they match your calculated values?

My Part 1:
`timescale îns/1ps module one_bit_full_adder(A,B,Cin,Sum,Cout);
input A,B,Cin;
output Sum,Cout;
wire w1,w2,w3;
// expressions for sum and carry out
// sum = a^b^cin;
// cout = a.b+b.cin+cin.a;
xor(Sum,A,B,Cin);
and(w1,A,B);
and(w2,B,Cin);
and(w3,Cin,A);
or(Cout,w1,w2,w3);
endmodule

testbench file:
timescale ins/ips
module testbench_one_bit_full_adder);
reg A, B, Cin; wire Sum, Cout;
one_bit_full_adder U1 (
A(A), B(B), Cin(Cin), Sum(Sum), Cout(Cout) );
initial begin
$dumpfile(test.vcd);
$dumpvars(0,testbench_one_bit_full_adder);
$monitor(A=%b, B=%b, Cin=%b | Sum=%b, Cout=%b, A, B, Cin, Sum, Cout);
end
initial begin
A = 0; B = 0; Cin = 0; #1; A = 0; B = 0; Cin = 1; #1; A = 0; B = 1; Cin = 0; #1; A = 0; B = 1; Cin = 1; #1; A = 1; B = 0; Cin = 0; #1; A = 1; B = 0; Cin = 1; #1; A = 1; B = 1; Cin = 0; #1; A = 1; B = 1; Cin = 1; #1;
$finish();
end
endmodule