Sketch a CMOS logic circuit that realizes the function Y=A+B(C+D)​, including both the pull-up and pull-down networks. Provide the W/L ratios for each transistor in the logic circuit. Assume that for the basic inverter n=2 and p=5 and that the channel length is 2μm. [n=(W/L)n​,p=(W/L)p​]