q1)Suppose that the device channels of a CMOS inverter are sufficiently wide to re- duce the high-to-low and low-to-high propagation delays to intrinsic levels. Assuming CL ≈ α(WN +WP) for such wide channels, and adopting α = 765 pF/m, determine the intrinsic delay for WP/WN = 5.

q2)A CMOS inverter drives 1.2-pF load capacitance at 45-MHz switching frequency, and
derives its energy from a battery storing 20 kJ. How many days does this operation last before
the battery needs to be recharged?