Consider the following two code snippets. The left one is a Verilog code, and the right one is its corresponding test bench. There are errors both in the design code and in the test bench. Correct the errors. Note that no other information is needed, and you can correct certain errors in any possible way that you find easier for you.

CODE 1
`timescale lns /1ps
module quiz(
input X,
input Y,

output reg F);

assign F = (X) & (Y)
endmodule

CODE 2
`timescale lns /1ps
module Quiz_1_Sim()
reg X_t;
reg Y_t;

reg F_t

Quiz_1 UUT(
.X(X_t),
.F(F_t));

intial
begin
X_t = 1'b0;
Y_t = 11'b00;

always #5 X_t = X_t;
always #10 Y_t =~ Y_t;
endmodule