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Question
Submitted by Jose W., Feb. 08, 2023, 03:07 p.m.

Consider the following instruction breakdown that decomposes an instruction into 4 parts:

OPCODE
DST
SRC
IMM

OPCODE specifies the Operation's CODE.
DST specifies a Destination register.
SRC specifies a Source register.
IMM specifies a 2's complement value (that's immediately available as part of the instruction).

Assume the architecture has 32-bit instructions, 121 opcodes, and 32 registers.

A.) What is the minimum number of bits required to represent an OPCODE?
B.) What is the minimum number of bits required to represent a register?
C.) What is the maximum number of bits that can be used to represent the IMM value?
D.) What is the largest positive value that can be represented by the IMM value?