Consider the following instruction sequence that runs on our MIPS 5-stage pipeline: ori $5, $0, 1
or $6, $0, $0
sll $2, $0, 31
srl $2, $0, 3
add $8, $4, $4
lw $9, 44($2)
beq $6, $7, exit
Assume that the instruction: ori $5,$0,1 is fetched in clock cycle 1. a) (3) During which clock cycle will the add $8,$4,$4 instruction read register $4 ? b) (3) In which pipeline stage does the instruction: lw$9, 44($2) compute the address of its memory operand? c) (3) What hardware unit or device within the pipelined data path is used to compute the branch target address for the beq $6, $7, exit intruction?
d) (3) If the beq $6, $7, exit instruction is fetched from memory address 0x40000008, what address will the PC register contain when this branch instruction is in the decode stage? e) (5) Assume that the beq $ 6, $7, exit instruction is fetched from memory address 0×40000008 and the low 16 bits of the instruction contain the pattern 0x8345. To what 32-bit memory address must the label exit correspond?